This invention relates to semiconductor devices, and particularly to a method of fabricating electrodes of such devices comprising layers of doped tungsten disilicide.
Various types of semiconductor devices, e.g., MOS devices, include electrodes formed from doped layers of polysilicon. Some of the layers are doped with N type impurities and others with P type impurities. The dopants greatly increase the electrical conductivity of the polysilicon. One prior art practice is to form a continuous layer of polysilicon and to implant ions of one type impurity into first portions of the layer while second portions of the layer are masked. Thereafter, the second portions are unmasked, and ions of the other type impurity are implanted into the second portions while the first portions are masked.
One problem with this process, particularly when used in the fabrication of gate electrodes overlying a thin oxide layer (formed on a surface of a semiconductor substrate), is that it is difficult to control the doping process for obtaining complete doping of the polysilicon layers while preventing penetration of the implanted ions into the underlying gate oxide layer.
A solution to this problem is to provide a layer of tungsten disilicide (WSi.sub.2) covering the polysilicon layer and to selectively implant the various ions into different portions of the WSi.sub.2 layer. WSi.sub.2 is an effective barrier against implanted ions whereby, using high energies and high ion concentrations, relatively large quantities of ions can be implanted into the WSi.sub.2 layer in short periods of time (desirable for reducing processing time), with no ions penetrating through the WSi.sub.2 and polysilicon layers into the underlying gate oxide layer. After the ion implantation processes, the semiconductor workpiece is annealed for diffusing the impurities in each portion of the WSi.sub.2 layer into the underlying polysilicon layer to form the differently doped polysilicon portions. Such annealing can be carefully controlled, whereby proper doping of the polysilicon portions occur with no significant penetration of the dopants into the gate oxide layer.
As above-explained, the ion implantation of the WSi.sub.2 layer is done selectively, using various masking layers, whereby different portions of the continuous layer of WSi.sub.2 are differently doped. Thereafter, the doping masking layers are removed and a new masking layer is applied which is patterned to expose those portions of the WSi.sub.2 layer which have not been doped during the ion implantation process. The new mask is then used as an etching mask in a process of selectively etching away the exposed, undoped portions of the WSi.sub.2 layer. The thus patterned WSi.sub.2 layer is then used as an etching mask for selectively patterning the underlying polysilicon layer, which is used, in turn, as an etching mask for selectively patterning the underlying gate oxide layer. The resulting patterned structures are the gate electrode structures of MOS devices subsequently to be formed in the semiconductor substrate.
However, another problem exists. Prior to the above-described selective patterning of the WSi.sub.2 layer, different portions of the layer had been doped with different conductivity type dopants for providing, eventually, two groups of gate electrode structures; one group being of N type conductivity and the other group being of P type conductivity. During the patterning process, during which holes or openings are formed through the WSi.sub.2 layer, the sides of the openings expose portions of the WSi.sub.2 layer which have been previously doped. The etching characteristics of WSi.sub.2, however, are a function of the doping thereof, with P type doped WSi.sub.2 having slightly different etching characteristics (in a given etching process) than N type doped WSi.sub.2. Thus, if the etching parameters are selected to provide optimum etching (in terms of minimum line widths and side surface contours) of one doped type of WSi.sub.2, the other doped type is not optimally etched. This results in at least one group of MOS devices having less than optimal structure and characteristics and degrades the quality of the semiconductor devices being made.
The present invention solves this problem.